1. Field of the Invention
The present invention generally relates to wiring boards, manufacturing methods of the wiring boards, and semiconductor packages. More specifically, the present invention relates to a wiring board including silicon and ceramic, a manufacturing method of the wiring board, and a semiconductor package.
2. Description of the Related Art
Conventionally, a semiconductor package where a semiconductor chip is mounted on a wiring board via a solder bump or the like has been known. In such a semiconductor package, the wiring board works as an interposer configured to connect the semiconductor chip and a mounting board such as a motherboard. An example of a related art semiconductor package having a wiring board as an interposer is discussed with reference to FIG. 1 through FIG. 3.
FIG. 1 is a cross-sectional view of an example of the related art semiconductor package. As shown in FIG. 1, in a semiconductor package 500, a semiconductor chip 200 is mounted on a substantially center part of a wiring board 100 via solder bumps 300 and is sealed by underfill resin 400.
The wiring board 100 has a structure of a first wiring layer 110, a first insulation layer 140, a second wiring layer 120, a second insulation layer 150, a third wiring layer 130 and a solder resist layer 160. The first wiring layer 110 and the second wiring layer 120 are electrically connected to each other via first via holes 140x provided in the first insulation layer 140. The second wiring layer 120 and the third wiring layer 130 are electrically connected to each other via second via holes 150x provided in the second insulation layer 150.
External connecting terminals 170 such as solder balls are formed on the third wiring layer 130 exposed in opening parts 160x of the solder resist layer 160. The first wiring layer 110 works as electrode pads to be connected to electrode pads 220 of the semiconductor chip 200. The external connecting terminal 170 works as a terminal to be connected to the mounting board such as the motherboard. It is general practice that the wiring board 100 has, due to limitations of a wiring width, a diameter of the via hole, and other factors, a multi-layer structure.
The semiconductor chip 200 includes a semiconductor substrate 210 and the electrode pads 220. The semiconductor substrate 210 has a structure where a semiconductor integrated circuit (not illustrated in FIG. 1) is formed on the substrate 210 made of, for example silicon (Si). The electrode pads 220 are formed on one side of the semiconductor substrate 210 and electrically connected to the semiconductor integrated circuit (not illustrated in FIG. 1).
The first wiring layer 110 of the wiring board 100 and the electrode pads 220 of the semiconductor chip 200 are electrically connected to each other via the solder bumps 300. The underfill resin 400 is supplied between a surface of the semiconductor chip 200 and a surface of the wiring board 100, the surfaces facing each other.
Next, a manufacturing method of the related art semiconductor package is discussed. FIG. 2 and FIG. 3 are views of examples of manufacturing steps of the related art semiconductor package. In FIG. 2 and FIG. 3, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
First, in a step illustrated in FIG. 2, the wiring board 100 and the semiconductor chip 200 manufactured by known methods are provided. A pre-solder 410 is formed on the first wiring layer 110 of the wiring board 100. A pre-solder 420 is formed on the electrode pads 220 of the semiconductor chip 200.
Next, in a step illustrated in FIG. 3, the first wiring layer 110 side of the wiring board 100 and the electrode pad 220 side of the semiconductor chip 200 are made to face each other so that the pre-solders 410 and 420 are positioned so as to face each other. Then, the pre-solders 410 and 420 are heated at, for example, approximately 230° C. so that the solders are melted and thereby the solder bumps 300 are formed.
Next, the underfill resin 400 is supplied between the surfaces facing each other of the semiconductor chip 200 and the wiring board 100 in a structural body illustrated at a lower side in FIG. 3, so that the semiconductor package 500 including the semiconductor chip 200 illustrated in FIG. 1 is completed. Since a warp may be formed at the wiring board 100 due to shrinkage on curing of the underfill resin 400, it is necessary for the wiring board 100 to have thickness greater than a certain thickness.
The semiconductor package 500 is connected to the mounting board such as the motherboard via the external connecting terminals 170. Thus, in the semiconductor package 500, the wiring board 100 works as an interposer configured to connect the semiconductor chip 200 and the mounting board such as the motherboard. See Japanese National Publication of International Patent Application No. 2003-503855.
However, in the development of down-sizing, miniaturization of the semiconductor chips is continuing. Therefore, minute wiring is required for the interposer where the semiconductor chip is mounted. Therefore, it becomes difficult to respond to the minute wiring required for the interposer by using the related art wiring board illustrated in FIG. 1. Because of this, although the interposers having a silicon base multi-layer structure which can correspond to the minute wiring are being studied, the cost of manufacturing equipment for achieving the required multi-layer structure is increasing so that the manufacturing cost is increased.